The present invention relates to a semiconductor device technique, and particularly to a technique effective when applied to a semiconductor device having a nonvolatile memory circuit section.
Of semiconductor devices, there is known one that has thereinside a nonvolatile memory circuit section for storing relatively small-capacity information such as information used upon trimming, relief and image adjustments of an LCD (Liquid Crystal Device), information about the production number of a semiconductor device, etc.
This semiconductor device having the nonvolatile memory circuit section has been described in, for example, Japanese Unexamined Patent Publication No. 2006-80247 (refer to a patent document 1). The following configuration of nonvolatile memory cell has been disclosed in the patent document 1. A floating gate electrode for storing an electric charge that contributes to storage of information is disposed in a main surface of a semiconductor substrate. The floating gate electrode has a portion relatively broad in width and a portion relatively narrow in width. The relatively broad portion of the floating gate electrode forms an electrode for a capacitive element. Part of the relatively narrow portion of the floating gate electrode serves as a gate electrode of an information write field effect transistor. Other part of the relatively narrow portion of the floating gate electrode serves as a gate electrode of an information read field effect transistor.
Further, a configuration in which a capacitance section, a write transistor and a read transistor are isolated by n wells, has been disclosed in, for example, FIG. 7 of U.S. Pat. No. 6,788,574 (patent document 2). A configuration in which write/erase is performed by an FN tunnel current has been disclosed in FIGS. 4A through 4C and columns 6-7 in the patent document 2.